Cerebras/open-register-design-tool
forked from Juniper/open-register-design-tool
Captured source
source ↗Cerebras/open-register-design-tool
Description: Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Language: Verilog
License: Apache-2.0
Stars: 1
Forks: 1
Open issues: 0
Created: 2017-11-08T21:35:30Z
Pushed: 2026-04-06T16:58:33Z
Default branch: master
Fork: yes
Parent repository: Juniper/open-register-design-tool
Archived: no
README:
open-register-design-tool
Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats: 1. SystemRDL - a stardard register description format released by Accellera.org 2. JSpec - a register description format used within Juniper Networks
The tool can generate several outputs from SystemRDL or JSpec, including:
- SystemVerilog/Verilog RTL code description of registers
- UVM model of the registers
- C++ and python models of the registers
- XML and text file register descriptions
- SystemRDL and JSpec (conversion)
Easiest way to get started with ordt is to download a runnable jar from the release area. Ordt documentation can be found here.