{"schema_version":"onlylabs.public_signal.v1","title":"OpenAI Job: Senior RTL Engineer, Interconnect Design","description":"OpenAI job signal with public source context, captured evidence pages, related signals, and data-business radar classification.","url":"https://onlylabs.fyi/signals/1ad19682-9038-4585-a525-d3b325083ffe","json_url":"https://onlylabs.fyi/signals/1ad19682-9038-4585-a525-d3b325083ffe/signal.json","generated_at":"2026-06-27T00:36:51.657Z","evidence_latest_fetched_at":"2026-06-24T07:04:52.868547+00:00","signal_first_seen_at":"2026-06-24T07:00:33.951981+00:00","org":{"slug":"openai","name":"OpenAI","category":"frontier-lab","category_label":"Frontier lab","dossier_url":"https://onlylabs.fyi/labs/openai","dossier_json_url":"https://onlylabs.fyi/labs/openai/dossier.json"},"related_urls":{"signal":"https://onlylabs.fyi/signals/1ad19682-9038-4585-a525-d3b325083ffe","signal_json":"https://onlylabs.fyi/signals/1ad19682-9038-4585-a525-d3b325083ffe/signal.json","source":"https://jobs.ashbyhq.com/openai/6cf91ff5-a811-435c-bf93-f3d958896599","lab_dossier":"https://onlylabs.fyi/labs/openai","lab_dossier_json":"https://onlylabs.fyi/labs/openai/dossier.json","analysis":"https://onlylabs.fyi/analysis/openai","analysis_json":"https://onlylabs.fyi/analysis/openai/analysis.json","analysis_evidence_json":"https://onlylabs.fyi/analysis/openai/evidence.json","category":"https://onlylabs.fyi/frontier","category_json":"https://onlylabs.fyi/frontier.json","category_feed":"https://onlylabs.fyi/frontier/feed.xml","category_signals_json":"https://onlylabs.fyi/signals.json","topic":"https://onlylabs.fyi/topics/hiring","topic_signals_json":"https://onlylabs.fyi/topics/hiring/signals.json","topic_feed":"https://onlylabs.fyi/topics/hiring/feed.xml","data_business":null},"answer_pack":{"answer":"OpenAI opened Senior RTL Engineer, Interconnect Design (San Francisco). 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The team is building next-generation AI-native silicon and infrastructure to support large-scale training and inference systems. Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production-quality silicon for OpenAI’s supercomputing infrastructure. ABOUT THE ROLE We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. 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